Along with the advancing of the generation of transistors, scaling by miniaturization is also being advanced constantly. On the roadmap of the ITRS (International Technology Roadmap for Semiconductor), it is expected that a gate length (Lg) of 20 nm or smaller will be achieved in transistors called the 32-nm node. The scaling needs to be advanced for Lg as well as for other parameters such as the equivalent oxide thickness (EOT) of a gate insulating film and the depth (Xj) of diffusion layers.
The above-described scaling of the EOT is effective for ensuring of the driving capability (Ids). However, the physical thickness of a silicon dioxide (SiO2)-based insulating film, which is used as a gate insulating film in related arts, is about to reach the limit, and therefore the technical difficulty in suppression of gate leakage is becoming particularly higher. This causes slowdown in the progression of the scaling after the generation of the 90-nm node. As a solution thereto, studies are being made on suppression of the depletion of a gate electrode through introduction of a High-k insulating film instead of the above-described SiO2-based insulating film and through introduction of a metal gate electrode instead of a poly-silicon (Poly-Si) gate electrode.
As the material of the above-described metal gate electrode, tungsten (W), titanium (Ti), hafnium (Hf), ruthenium (Ru), iridium (Ir), or the like is used. These metals are highly-reactive materials. Therefore, when being subjected to high-temperature heat treatment, these metals react with a gate insulating film and so on, which causes the deterioration of the film quality of the gate insulating film. Consequently, it is desirable that high-temperature heat treatment be not performed after formation of the metal gate electrode. As one method to realize this desire, a dummy gate process (damascene gate process) has been proposed (refer to e.g. Japanese Patent Laid-open No. 2000-315789 and Japanese Patent Laid-open No. 2005-26707).
The dummy gate process has the following process flow. Specifically, initially a dummy gate is formed on a silicon substrate by using Poly-Si or the like, followed by formation of diffusion layers such as source/drain regions and extension regions. Thereafter, an interlayer insulating film is formed, and then the upper face of the dummy gate is exposed by a chemical mechanical polishing (CMP) method. Subsequently, the dummy gate is removed, so that a trench (recess) for burying a gate material therein is formed in a self-aligned manner. If after the formation of the trench, a gate insulating film for a transistor is formed and immediately thereafter a metal gate electrode is buried in the trench, heat treatment required for activation of the diffusion layers is unnecessary after the formation of the metal gate electrode, and hence subsequent processing steps can be carried out at a low temperature.
Meanwhile, a large number of techniques that allow enhancement in the driving capability without relying on the scaling have also been proposed in recent years. In these techniques, the driving capability is enhanced by applying stress to a channel region to thereby increase the mobility of electrons and holes (refer to e.g. T. Ghani et al., International Electron Devices Meeting Technical Digest, 2003, p. 987).
A description will be made below about an example in which this mobility enhancement technique is applied to a method for manufacturing a p-type field effect transistor (PMOS transistor) by use of the sectional views of FIGS. 21 and 22, which show manufacturing steps.
Referring initially to (a) of FIG. 21, element isolation regions (not shown) are formed on the surface side of a silicon (Si) substrate 101. Subsequently, over the Si substrate 101, a gate electrode 103 composed of Poly-Si is pattern-formed with the intermediary of a gate insulating film 102 composed of SiO2. At this time, the respective material films for forming the gate insulating film 102 and the gate electrode 103, and a hard mask 104 formed of a silicon nitride (SiN) film are stacked over the Si substrate 101, and then the hard mask 104 and the gate electrode 103 are pattern-etched.
Subsequently, as shown in (b) of FIG. 21, offset spacers 105 formed of a SiN film are formed on both the sides of the gate insulating film 102, the gate electrode 103, and the hard mask 104. Referring next to (c) of FIG. 21, sidewalls 106 composed of SiO2 are formed on both the sides of the gate insulating film 102, the gate electrode 103, and the hard mask 104, for which the offset spacers 105 have been provided.
Subsequently, as shown in (d) of FIG. 21, by using the gate electrode 103 as a mask, for which the hard mask 104 has been provided thereon and the sidewalls 106 have been provided on both the sides thereof with the intermediary of the offset spacers 105, the Si substrate 101 is partially removed by etching, i.e., so-called recess etching is performed, to thereby form recess regions 107. Thereafter, a natural oxide film on the surface of the Si substrate 101 is removed by cleaning treatment with a dilute hydrofluoric acid.
Subsequently, as shown in (e) of FIG. 22, on the recess regions 107, i.e., on the surface of the partially etched part of the Si substrate 101,  mixed crystal layers 108 formed of a silicon germanium (SiGe) layer doped with a p-type impurity are epitaxially grown. Thereby, these mixed crystal layers 108 will serve as the source/drain regions, and the region in the Si substrate 101 between the source/drain regions and directly beneath the gate electrode 103 will serve as a channel region Ch. The mixed crystal layers 108 are composed of Si and Ge having a lattice constant larger than that of Si. Therefore, compressive stress is applied to the channel region Ch interposed between the mixed crystal layers 108, so that strain arises in the channel region Ch.
Thereafter, as shown in (f) of FIG. 22, the sidewalls 106 (see above-described (e) of FIG. 22) are removed, so that the surface of the Si substrate 101 on both the sides of the gate electrode 103 provided with the offset spacers 105 is exposed.
Referring next to (g) of FIG. 22, ion implantation is performed for the Si substrate 101 on both the sides of the gate electrode 103 provided with the offset spacers 105 by using the offset spacers 105 and the hard mask 104 as the mask, to thereby form extension regions 109.
Subsequently, as shown in (h) of FIG. 22, sidewalls 110 composed of SiN are newly formed on both the sides of the offset spacers 105. Thereafter, by wet etching, the hard mask 104 (see above-described (g) of FIG. 22) is removed to expose the surface of the gate electrode 103, and a natural oxide film on the surfaces of the mixed crystal layers 108 is removed.
Subsequently, a refractory metal film such as a nickel film is deposited across the entire surface of the Si substrate 101, including on the mixed crystal layers 108, in such a manner as to cover the gate electrode 103, for which the sidewalls 110 have been provided on both the sides thereof with the intermediary of the offset spacers 105. Thereafter, heat treatment is performed to thereby turn the surface sides of the gate electrode 103 and the mixed crystal layers 108 into a silicide, so that silicide layers 111 composed of a nickel silicide are formed. This decreases the resistance of the surface side of the source/drain regions, and thus reduces the contact resistance.
In the above-described manner, by straining the channel region Ch through application of compressive stress to the channel region Ch from the mixed crystal layers 108, a PMOS transistor having sufficiently-high carrier mobility can be obtained.
In addition, although not shown in the drawings, in the case of forming an n-type field effect transistor (for example, an NMOS transistor), a silicon carbide (SiC) layer composed of Si and carbon (C) having a lattice constant smaller than that of Si is epitaxially grown as the mixed crystal layers 108 on the recess regions 107, to thereby apply tensile stress to the channel region Ch. This strains the channel region Ch, which can provide an NMOS transistor having sufficiently-high carrier mobility.
Furthermore, there has also been disclosed a method in which the above-described damascene gate process is used and a SiGe layer is formed on recess regions on both the sides of a gate electrode by a selective CVD (Chemical Vapor Deposition) method (refer to e.g. Japanese Patent Laid-open No. 2004-31753).
However, in the above-described method for manufacturing the PMOS described by using FIGS. 21 and 22, referring to the plan view of (a) of FIG. 23 and the sectional view of (b) of FIG. 23, compressive stress (arrowheads A) is applied to the channel region Ch from the mixed crystal layers 108 formed of a SiGe layer. By this stress, in the xy plane, escaping force (arrowheads B) works in the directions perpendicular to arrowheads A. In addition, along the direction of the normal of the Si substrate 101 (z direction), escaping force (arrowheads C) works toward the outside of the Si substrate 101. Thus, if the gate electrode 103 composed of Poly-Si exists over the channel region Ch in the Si substrate 101, the escaping force (arrowheads C) toward the outside of the Si substrate 101 is suppressed by counteraction (arrowheads D) from the gate electrode 103. This precludes sufficient application of compressive force to the channel region Ch, and hence suppresses enhancement in the carrier mobility.
Furthermore, also in the above-described method for manufacturing the PMOS, referring to the plan view of (a) of FIG. 24 and the sectional view of (b) of FIG. 24, compressive stress (arrowheads A′) is applied to the channel region Ch from mixed crystal layers 108′ formed of a SiC layer. By this stress, in the xy plane, escaping force (arrowheads B′) works in the directions perpendicular to arrowheads A′. In addition, along the direction of the normal of the Si substrate 101 (z direction), escaping force (arrowheads C′) works toward the inside of the Si substrate 101. Thus, if the gate electrode 103 composed of Poly-Si exists over the channel region Ch in the Si substrate 101, the escaping force (arrowheads C′) toward the inside of the Si substrate 101 is suppressed by counteraction (arrowheads D′) from the gate electrode 103. This precludes sufficient application of compressive force to the channel region Ch, and hence suppresses enhancement in the carrier mobility.
Furthermore, to enhance the effect of the stress, it is effective to increase the Ge concentration in the mixed crystal layers 108 formed of a SiGe layer in the PMOS transistor and increase the C concentration in the mixed crystal layers 108′ composed of SiC in the NMOS transistor. However, if the germanium (Ge) concentration or the carbon (C) concentration is too high, defects will occur at the interface between the Si substrate 101 and the mixed crystal layers 108 or the mixed crystal layers 108′. This will result in the occurrence of problems such as the lowering of the stress and increase in junction leakage.
On the other hand, in the method described in Japanese Patent Laid-open No. 2004-31753, in which a SiGe layer is formed on recess regions by a selective CVD method, compressive stress to a channel region does not arise because the SiGe layer is formed by the selective CVD method. In addition, the SiGe layer is formed also in an NMOS region, and thus tensile stress to a channel region does not arise.
Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device and a semiconductor device, each allowing prevention of crystal defects due to the existence of a high concentration of atoms having a lattice constant different from that of Si in a mixed crystal layer, and each permitting sufficient application of stress to a channel region.